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Sun星期日日曜日
08.30
2026
https://ethresear.ch/t/same-instruction-count-23x-the-wall-clock-working-set-effects-in-a-deterministic-risc-v-interpreter/25856
The author measures execution cost in a deterministic RISC-V interpreter and finds up to 23x wall-clock time differences for the same step count across instruction mixes and memory access patterns. Step counting alone cannot tightly bound physical cost, and performance ordering can reverse across machines, challenging protocol-level execution budgets.作者在 deterministic RISC-V 解释器中测量执行成本，发现相同步数下不同指令混合和内存访问模式可导致高达23倍的墙钟时间差异。文章强调，仅靠步数无法紧致约束物理执行成本，且跨机器性能排序会反转，对协议级执行预算提出挑战。決定論的RISC-Vインタプリタで実行コストを測定し、同一ステップ数でも命令ミックスやメモリアクセスパターンにより最大23倍の実行時間差が生じることを示した。ステップ数だけでは物理コストを厳密に拘束できず、マシン間で性能順位が逆転する可能性があり、プロトコルレベルの実行予算に課題を投げかける。
NotesNotes要点
- Pointer-chasing load is 23x slower than reference load at the same step count.
- Opcode identity alone cannot distinguish sequential load from pointer-chasing, as their instruction streams are identical.
- Working set size affects execution time, with a cliff determined by host cache hierarchy, not intrinsic to the program.
- Desktop can be slower than phone at large working sets, so worst-case hardware is not necessarily low-end.
- The author invites community to run benchmarks and collect cross-CPU data to verify performance ordering reversals.
- Scope is limited to native interpreter execution cost, not ZK proving cost.
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Sun星期日日曜日
08.30
2026
